基于统计分析的SoC定点硬件加速器字长设计

Design of Fixed-point Hardware Accelerator Word Length in SoC Based on Statistical Analysis

在由通用RISC处理器核和附加定点硬件加速器构成的定点SoC(System-on-Chip)芯片体系架构基础上,提出了一种新颖的基于统计分析的定点硬件加速器字长设计方法。该方法利用统计参数在数学层面上求解计算出满足不同信噪比要求下的最小字长,能有效地降低芯片面积、功耗和制作成本,从而在没有DSP协处理器的低成本RISC处理器核SoC芯片上运行高计算复杂度应用。

This paper proposes a novel method for designing the fixed-point hardware accelerator word length based on statistical analysis and outlines a good architecture for real-time low cost SoC(System-on-Chip) designs with a generic RISC(Reduced Instruction Set Computer) processor core and extra hardware accelerator needed in order to implement high computational cost calculations without a digital signal processor.The fundamental execution unit of hardware accelerator is a custom-designed fixed-point processing ...