基于CPLD的高速面阵CCD驱动电路设计

Design of CPLD-based High Speed Area Array CCD Driving Circuit

着重介绍了基于CPLD来设计产生高速面阵IA-D1CCD芯片复杂驱动时序和整个CCD相机的电子系统控制逻辑时序。同时采用CCD视频处理专用集成芯片处理CCD输出信号,提高了图像信噪比,改善了图像质量。使用结果表明:该硬件电路结构简单、成本低廉、可靠性高、功耗较低,并满足了工程项目小型化的要求。

A design method is introduced for the complex driving timer of high speed area array CCD and for the control logic timer of the whole electronic system of the CCD camera, based on CPLD. At the same time, the CCD output video signal was processed by adopting specific integrated circuit (ASIC) for CCD video signal processing, so that both the signaltonoise ration and the image quality are improved. The result indicates that the circuit is characterized by simple framework, lowl cost, high reliabili...