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一种基于遗传算法的SoC测试调度方法 被引量:6

An Test Scheduling Method of SoC based on Genetic algorithm
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摘要 文章提出了一种基于遗传算法的SoC测试调度方法,通过该方法可以有效地优化测试总线的划分,合理地调度各个芯核以实现并发测试,能够有效的缩短芯核地测试时间。该算法把测试调度问题的可行解集用种群表示,从初始种群开始,按照适者生存、优胜劣汰的原理,逐代演化产生出越来越好的近似解。文章详细分析了该算法过程,对2002年国际测试会议(ITC′02)所提供的SOC国际基准电路进行测试调度实验,实验结果表明,此算法比传统的整线性规划(ILP)算法的结果要优化。 This paper proposes a SoC test scheduling based on genetic algorithm which can efficiently optimize the division of testing bus,reasonably schedule each core to realize parallel test,and efficiently short the test time of core.Representing feasible solution of test scheduling with population,based on "survival of the fittest",and beginning with the initial population,This algorithm evolves by generation to produce approximation solution.Utilizing international reference circuit provided by International Tes...
作者 雷加 方刚
出处 《仪器仪表学报》 EI CAS CSCD 北大核心 2007年第S1期15-17,43,共4页 Chinese Journal of Scientific Instrument
基金 广西省自然科学基金(0542050)资助项目
关键词 遗传算法 测试优化 测试调度 genetic algorithm test optimization test scheduling
  • 相关文献

参考文献1

  • 1Vikram Iyengar,Krishnendu Chakrabarty,Erik Jan Marinissen. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip[J] 2002,Journal of Electronic Testing(2):213~230

同被引文献53

  • 1雷加,苏波.基于IEEE1149.4标准TAP控制器的设计[J].仪器仪表学报,2007,28(S1):298-299. 被引量:9
  • 2赵红军,杨日杰,崔坤林,崔旭涛,王小华.边界扫描测试技术的原理及其应用[J].现代电子技术,2005,28(11):20-24. 被引量:12
  • 3杨军,罗岚.基于TCG图和模拟退火算法的SoC测试调度[J].电路与系统学报,2006,11(5):37-43. 被引量:1
  • 4CHAKRABARTY K. Optimal test access architectures for system-on-a-chip[ J]. ACM Trans. Design Automation of Electronic System ,2001,6 ( 1 ) :26-49.
  • 5ZHAO D, UPADHYAYA S. Dynamically partitioned test scheduling with adaptive TAM configuration for powerconstrained SoC testing[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005,24 (6) :956-965.
  • 6WEI Z, REDDY S M, POMERANZ I, et al. SoC test scheduling using simulated annealing[ C ]. Proceedings of IEEE VLSI Test Symposium. Napa Valley, California,2003 : 325-330.
  • 7GUO P N, CHENG C K, YOSHIMURA T. An O-tree representation of non-slicing floorplan and its applications [ C]. Proc. DAC, LosAngeles, 1999:268-273.
  • 8CHANGYC,CHANGYW,WU GM, et al. Wu. B^*- Trees: A new representation for non-slicing floorplans [ C ]. DAC, California, 2000:458-463.
  • 9VIKRAM I, KRISHNENDU C, ERIK J M. Test wrapper and test access mechanism co-optimization for system-onchip [ C ]. International Test Conference. Baltimore, 2001 : 1023-1032.
  • 10HO A J, KANG S. SoC test scheduling algorithm using ACO-based rectangle packing [ C ]. International Conference on Intelligent Computing, Kunming, 2006 : 655-660.

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