期刊文献+

基于gm/ID参数的运算放大器设计 被引量:3

Design of Amplifiers Based on gm/ID Parameter
下载PDF
导出
摘要 介绍一种基于gm/ID参数特性的模拟电路优化设计方法,并以CMOS密勒补偿运算放大器的设计为例具体阐述该方法的基本设计步骤.该方法以统一的gm/ID与ID/(W/L)的关系曲线为基本设计出发点,综合电路的其它设计要求,而提出的一种优化性能指标的设计思路.对所设计的运算放大器模拟仿真验证了这种方法的有效性. The aim of this paper is to present a transistor optimization methodology for analog integrated CMOS circuits,based on the physics-based gm/ID characteristics,This method dependents curve of gm/ID and ID/(W/L)in all operations regions are integrated with other design specifications,providing solutions close to the optimum.As an example,we show the results obtained for the design of a CMOS Miller operational Transconductance Amplifier,Experimental results are presented,in order to validate the methodology.
机构地区 东南大学
出处 《电脑知识与技术(过刊)》 2007年第16期1020-1022,共3页 Computer Knowledge and Technology
关键词 运算放大器 CMOS gm/ID Operationa Amplifier CMOS gm/ID
  • 相关文献

参考文献4

  • 1[1]Allen PE,Holerg DR.CMOS analog circuit design.Oxford University Press;2002.
  • 2[2]F.P.Cortes,E.Fabris,S.Bampi,"Analysis and dsign of amplifiers and comparators in CMOS 0.35um technology",Microelectronics Reliability,Eselvier Ltd,April 2004,vol.44,p.675-664.
  • 3[3]F.Silveira.D.Flandre,and P.G.A.Jespers " A gm/ID Based Methology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of Silicon-on-Insulator Micropower OTA" IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.31,NO.9,SEPIEMBER 1996.
  • 4[4]毕查德,拉扎维.陈贵灿,程军,张瑞智.等译.模拟CMOS集成电路设计[M].西安交通大学出版社,2004.

同被引文献25

  • 1殷湛,郭立,杨吉庆.一种用于ADC模拟集成电路设计和分析的MOS晶体管模型[J].计算机工程与科学,2006,28(8):105-107. 被引量:1
  • 2AKURAI S, ISMAIL M. Robust design of rail to rail CMOS operational amplifiers for a low power supply voltage [ J ]. IEEE J. Solid State Circuits, 1996,31 (2) : 146 - 156.
  • 3HOGERVORST R, TERO J P, HUIJSING J H. Compact CMOS constant gm rail to rail input stages with g,. controlled by an e- lectronic Zener diode [ J ]. IEEE J. Solid State Circuits, 1996,31 (7) : 1035 - 1040.
  • 4WANG M, MAYHUGH T L, EMBABI Jr S H K. Constant gm rail to rail CMOS op-amp input stage with over-lapped transition regions [ J]. IEEE J. Solid State Circuits, 1999,32(10) : 148 - 156.
  • 5HOGERVORST R, TERO J P, ESCHAUZIER R G H. Compact power efficient 3 V CMOS rail to rail input/output op-amp for VLSI cell libraries[ J]. IEEE J. Solid State Circuits, 1994,29(12) : 1505 - 1513.
  • 6LIANG Yung-chinh, SHEU Meng-lieh, Hsu Wei-hung. A rail to rail, constant gain CMOS op-amp Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Tainan, December 6- 9, 2004 [ C]. New Jersey: Piscataway,2004, 1:257 - 260.
  • 7NAGARAJ K. Constant trans conductance CMOS amplifier input stage with rail to rail input common mode voltage[ J]. IEEE Trans. Circuits Systems II, 1995,42 (5) : 366 - 368.
  • 8ZHAO Wu, FU Rui, ZHANG Zhi-yong, et al. Design of a rail to rail constant g,, CMOS operational amplifier Proceedings of the 2009 WRI World Congress on Computer Science and Information Engineering, Los Angeles, March 31 -April 2,2009 [ C ]. New Jersey: Piscataway,2009,6 : 198 - 201.
  • 9拉扎维.模拟CMOS集成电路设计[M].陈贵灿,译.西安:西安交通大学出版社,2003.
  • 10Cunha A I A,Schneider M C,Muntoro C G. An MOS Transistor Model for Analog Circuit Design[J]. IEEE J.of Solid-State Circuits, 1998,33(10) : 1510-1519.

引证文献3

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部