基于FPGA的32阶FIR滤波器设计

Design of 32 Order FIR Filter based on FPGA

研究了一种采用FPGA实现32阶FIR数字滤波器硬件电路方案;讨论了窗函数的选择、滤波器的结构以及系数量化问题;研究了FIR滤波器的FPGA实现,各模块的设计以及如何优化硬件资源,提高运行速度等问题。实验结果表明了该方法的有效性。

To study method to implement 32 order FIR filter based on FPGA in this paper;With the design,how to select the windows function,struct and coefficients for FIR filter,how to accelerate the operation and optimize the availability of hardware resource are discussed.The example shows that the proposed method is feasible and efficient.