基于CSL架构的低功耗CMOS环型振荡器的设计

A Low-power CMOS Ring-Based Oscillator Using Current Steering Logic Structure

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摘要该文设计了一种基于电流控制逻辑架构的1.8GHz低功耗环型压控振荡器,分析了p型电流控制逻辑,并作为环振的延迟单元。该环型振荡器采用SMIC 0.18μm CMOS工艺实现。在1.8V电压下,具有大于1GHz的调谐范围,相位噪声为-96.4dBc/Hz@3MHz,功耗是1.40mW。与其他已报道的类似结构相比,该设计具有更好的性能。 A completely integrated 1.8GHz low-power ring-based voltage-controlled oscillator(VCO) is designed in SMIC 0.18μm CMOS process by using p-type current steering logic(CSL) structure as the delay cell.With single 1.8V supply,it has a tuning range of 1GHz and a phase noise of-96.4dBc/Hz at 3MHz offset from center frequency through out the tuning range.The total power consumption is 1.40mW.Comparison shows that this design has better performance than previously published similar results.

作者周海峰韩雁

机构地区浙江大学微电子与光电子研究所

出处《杭州电子科技大学学报（自然科学版）》 2007年第5期34-38,共5页 Journal of Hangzhou Dianzi University：Natural Sciences

关键词低功耗电流控制逻辑压控振荡器 low power current steer logic VCO

分类号 TN752 [电子电信—电路与系统]

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杭州电子科技大学学报（自然科学版）

2007年第5期

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基于CSL架构的低功耗CMOS环型振荡器的设计

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