三阶级联ΣΔ调制器的行为级建模

Behavioral Modeling of Third-order Cascaded Sigma-delta Modulators

基于高阶ΣΔ调制的过采样调制器为超大规模集成电路中的高分辨率模拟-数字转换提供了一种有效方法。该文探讨一种用于数字音频模数转换器的CMOSΣΔ调制器的设计。采用一种三阶级联的结构,具有输入范围和动态范围大的特点。利用MATLAB SIMULINK对时域的行为级仿真做了研究,并考虑到了级联结构中的失配效应。除此之外,该调制器在SMIC 0.18μmCMOS工艺下实现,经过了SPICE仿真的验证。通过对比行为级仿真结果和器件级仿真结果,找到了一条能足够精确并快速仿真级联ΣΔ调制器的途径。在44.1 kHz的奈奎斯特转化频率下,仿真中的调制器达到了111dB的动态范围。

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high resolution analog-to-digital conversion in a VLSI technology.This paper examines the design of a CMOS sigma-delta modulator for digital-audio A/D conversion that operates from a single 3V supply. A third-order cascaded architecture is introduced for its large full-scale input range and dynamic range.Time-domain behavioral simulation considering the mismatch effects in the cascaded architecture is explored based on MATLAB SIMULINK.The modulator is also validated by SPICE simulation,based on SMIC 0.18um process.By comparing the results from behavioral models and device models,we find a fast and accurate enough approach for the simulation of cascaded sigma-delta modulators.The experimental modulator achieves a dynamic range of 111dB at a Nyquist conversion rate of 44.1 kHz.