摘要
针对目前已有的高层电路模型普遍没有很好的同时体现描述的可控性和可观性,本文从时序电路RTL行为描述抽象出一种CRG电路模型。并在此模型上直接对其进行测试生成或可测试性分析等计算机辅助测试。试验表明,该模型和算法是有效的。
For the high-level circuit models proposed up to now, the controllability and the observability can not behave to band together very well. This paper proposes a circuit model, which is obtained from sequential circuits’RTL behavioral description. CAT is carried out based on it, ex. effective ATPG or testability analysis. Experimental results demonstrate the effectiveness of this model and the algorithm.
出处
《中国集成电路》
2006年第11期61-65,共5页
China lntegrated Circuit
关键词
电路模型
寄存器传输级
行为描述
硬件描述语言
自动测试图形生成
circuit model
register transfer level
behavioral description
hardware discription language
automatic test pattern generation