摘要
论文提出了一种可同时实现模2~n±1乘法的算法及其VLSI结构。通过对常规并行前缀加法器和乘法器的改造,在实现普通加法和乘法的基础上增加少量逻辑,实现了模2~n±1乘法(n=8、16、32)。较之同类设计,该设计实现了对常规加法器和乘法器资源的高度重用,而且性能较高。
An algorithm on implementation of modulo 2n ±1 multiplication simultaneously and its VLSI structure are proposed. By reconstructing conventional parallel prefix adder and multiplier, and by adding a few logic on the basis of implementation of common addition and multiplication, modulo 2n ± 1(n=8, 16, 32) multiplication is implemented. This design makes a high reuse of the adder and multiplier resource and is of high performance as compared with others in the same category.
出处
《信息安全与通信保密》
2008年第2期97-99,共3页
Information Security and Communications Privacy
