基于FPGA的高速RS编解码器设计与实现

Design and Realization of High Speed RS Codec Based on FPGA

本文详细介绍了RS(255,191)编解码器的设计,按照自上而下的设计流程给出了算法的FPGA实现。根据编解码器的不同特点,采用不同方法实现GF(28)乘法器。编码器采用并行结构、解码器采用并行无逆的BM算法实现关键模块,求逆器采用查表方法。在资源占用允许的同时最大限度提高编解码速度。

This paper introduces the design of RS(255,191)codec.The algorithm is obtained from FPGA in terms of up-down design flow.According to different features of codec,different methods is used to realize GF(28)multiplexer.Encode adopts parallel architecture,de- coder adopts parallel non-inversion BM algorithm to achieve key module,Check the con- tradictory to matrix for the inversion,thus greatly improving the encoding and decoding speed with allowable resources occupation.