分组密码算法的三种硬件实现结构及性能分析

Three Hardware Implementation Structures for Block Ciphers and Performance Analysis

针对分组密码算法,研究了反复循环、循环展开和流水线三种实现结构,分析了三种结构下系统的资源占用、吞吐率、最高工作频率等参数,以求在各种不同应用环境,找出满足其需求的实现方案。以3DES为例分别实现了这三种结构,最后给出了基于Altera公司的CYCLONE系列FPGA的实现结果,对结果进行了比较和分析。

Block ciphers are all comprised of a basic looping structure. Based on this looping structure of block ciphers, this paper studies the following three architecture options, that is, iterative looping, loop unrolling and partial pipelining, analyzes the performance parameters of the three implementations structures and then discusses three implementation options on 3DES algorithm respectively. Finally it analyzes the implementation result based on the FPGA of the CYCLONE family of Altera corporation.