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基于异步电路技术改进三模冗余结构 被引量：1

Modified Triple Modular Redundancy Structure Based on Asynchronous Circuit Technique
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摘要 在借鉴异步电路技术的基础上,对传统三模冗余(TMR)结构进行了改进,提出了基于异步C单元的双模冗余(DMR)结构和基于DCTREG的时空三模冗余(TSTMR-D)结构. DMR结构每位只需两个冗余单元,并采用异步C单元对冗余单元的输出进行同步. TSTMR-D结构采用解同步电路中显式分离主从锁存器的结构,可以广泛用于各种流水线.在SMIC 0.35μm工艺下分别以DMR,TMR和TSTMR-D结构实现了3个容错8051内核.错误注入实验结果表明,与TMR结构相比,DMR结构可以减小芯片面积,提高芯片性能,同时具有容时序逻辑SEU的特性. TSTMR-D结构在恰当的面积和延迟开销下,可以对各种类型的电路结构进行全面的SEU和SET防护.
作者 龚锐 陈微 刘芳 戴葵 王志英
机构地区 国防科学技术大学计算机学院
出处 《计算机研究与发展》 EI CSCD 北大核心 2006年第z2期23-27,共5页 Journal of Computer Research and Development
基金 国家自然科学基金项目(90407022)
关键词 三模冗余 异步电路 双模冗余 时空三模冗余 容错 容SEU 容SET
分类号 TP302.8 [自动化与计算机技术—计算机系统结构]
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参考文献10

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共引文献3

同被引文献11

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  • 2高星,廖明宏,吴翔虎,黄振远.基于虚拟寄存器的控制流错误检测算法[J].宇航学报,2007,28(1):183-187. 被引量：4
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计算机研究与发展
2006年 第z2期

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