摘要
在大量仿真数据以及当前集成电路设计工艺的基础上,提出了一种简单互连线负载的有效电容计算模型.该模型基于精确的互连线π模型,考虑了互连线电阻对负载互连线的屏蔽作用,并能与目前常用的器件时延公式兼容.实验结果表明,该模型与电路模拟软件SPICE仿真结果相比较误差小于1.2%.
A simple and efficient model was presented for computing the effective capacitance of interconnect load based on simulation and integrated circuit process.The method which is based on accurate π model and accounts for the shielding effect of the interconnect resistance is compatible with the empirical delay model of devices. The experimental results show that the model is accurate and within less than 1.2% error compared with SPICE.
出处
《上海交通大学学报》
EI
CAS
CSCD
北大核心
2004年第z1期115-117,共3页
Journal of Shanghai Jiaotong University
基金
国家自然科学基金资助项目(90207010)
关键词
集成电路
有效电容
深亚微米
互连线
门级时延
integrated circuits
effective capacitance
deep sub-micron
interconnect
gate delay