摘要
本文主要叙述了半导体集成电路在封装过程中,环境因素和静电因素对IC封装方面的影响,同时对封装工艺中提高封装成品率也作了一点探讨。
The effects of environmental and electrostatic factors on IC packaging are mainly stated in this paper, Meanwhile the improvement of the product field in IC packaging is also offered。
出处
《电子与封装》
2003年第1期43-48,59,共7页
Electronics & Packaging
关键词
环境因素
静电防护
封装
Environmental factors
Eletrostatic protection
packaging
