基于VHDL的数字时钟设计

VHDL是一种标准的硬件描述语言,该语言可以描述硬件电路的功能、信号连接关系及定时关系,是当今电子设计自动化(EDA)的核心技术。本文通过简易电子表的设计实例,详细介绍了利用VHDL设计电路的流程和方法。

VHDL is a standard hardware description language, it can describe the function of the hardware circuitry, signal connection relations and regular relations, and it is the electronic design automation (EDA) the core technology. Through simple examples of the design of electronic clock, details on the use of VHDL circuit design processes and methods.