摘要
This paper is a case study of a structured Design for Test (DFT) methodology that was adopted for our ASIC project used in High Definition TV system. The methodology includes the following features, full scan for chip test, test point insertion, test, path delay test, embedded SRAM Build In Self Test (BIST), and also the implementation of IEEE 1149 1 Standard. The paper discusses details of the ASIC designs and technology. Our chip has a 2+ million transistors and large embedded memory, which brought us extra test challenge.
This paper is a case study of a structured Design for Test (DFT) methodology that was adopted for our ASIC project used in High Definition TV system. The methodology includes the following features, full scan for chip test, test point insertion, test, path delay test, embedded SRAM Build In Self Test (BIST), and also the implementation of IEEE 1149 1 Standard. The paper discusses details of the ASIC designs and technology. Our chip has a 2+ million transistors and large embedded memory, which brought us extra test challenge.
