期刊文献+

模拟集成电路模块生成系统的电气性能研究

Electrical Property Analysis of the Module Generator Environment for Analog Integrated Circuits
下载PDF
导出
摘要 文章对模拟集成电路模块生成系统的电气性能进行了系统研究 ,如 MOS晶体管失配量、栅极 RC常数、寄生电容及路径载流等。并将各电气参数的估算值与具体应用相结合 ,控制不同限制条件及应用背景下的模块生成 ,增强电路设计的可靠性。采用该电气性能驱动的模块生成系统 ,已经辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图。 This paper analyzes the related electrical properties of the module generator environment for analog integrated circuits, such as transistor mismatching, RC time constant of MOS transistor gates, parasitic capacitance and electromigration The estimation of electrical properties was taken into consideration during the module generation in order to satisfy the different constraints and application requirements It enhances the reliability of circuit design A number of high quality operational amplifiers and analog switches have been designed with the help of this electrical property driven module generator environment
出处 《微电子学》 CAS CSCD 北大核心 2002年第5期321-324,329,共5页 Microelectronics
基金 德国撒克森 -安亥州和西门子公司资助
关键词 电气性能 模块生成系统 模拟集成电路 Electrical property Module generation environment Analog integrated circuit
  • 相关文献

参考文献7

  • 1[1]Gielen G, Gebyser G, Lampaert K, et al. An analogue module generator for mixed analogue/digital ASIC design [J]. Int J Circ Theory and Applications,1995; 23(8): 269-283.
  • 2[2]Phelps R, Krasnicki M, Rutenbar R. et al. Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search [J]. IEEE Trans Comp Aid Des Integ Circ &Syst, 2000; 19(6): 703-717.
  • 3[3]Zhang L, Kleine U, Roewer F, et al. A novel design tool for analog integrated circuits [A]. Proc 1st Joint Symp Opto- & Mircoelectronic Dev Circ [C]. Nanjing, Southeast Univ Press. 2000. 146-149.
  • 4[4]Wolf M, Kleine U. Automatic topology optimization for analog module generators [A]. Proc European Des & Test Conf [C]. Paris:EDTC Press. 1998. 961-962.
  • 5[5]Lakshmikumar K R. Characterization and modeling of mismatch in MOS transistors for precision analog design[J]. J Sol Sta Circ, 1986; 21 (6): 1057-1086.
  • 6[6]Bastos J. Mismatch characterization of small size MOS transistors [A]. Proc IEEE Int Conf Microelectronic Test Structures [C]. Nara: IEEE Press.1995. 271-276.
  • 7[7]Wolf M , Kleine U . Application independent module generation in Analog Layouts [A]. Proc European Design & Test Conf [C]. Paris: EDTC Press. 1997.624.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部