2[2]Hussein A I. Design and verification technique used in a graduate level VHDL course [A]. 29th ASEE/IEEE Frontiers in Education Conference [C]. 1999.
3[3]Erdogan A T, Arslan T. Low power scheme for FIR filter implementation on single multiplier CMOS DSP processors [J]. IEEE Electronic Letters, 1996; 32(21): 1959-1960.