SDH中E1接口数字分接复用的ASIC电路设计与实现

ASIC Design and FPGA Implement of the Digital Multiplexer and Demultiplexer in SDH

介绍了用于SDH系统中E1接口电路———数字分接复用器的专用集成电路 (ASIC)的VHDL电路设计及FPGA实现。该分接复用器电路用纯数字同步方式实现 ,可完成SDH系统接口电路中 7路 (可扩展成N路 )E1数据流的分接和复用。该设计输入采用VHDL和状态转移图。

This paper introduces the VHDL design and FPGA implement of the digital multiplexer and demultiplexer in SDH E1 interface circuit. This design is implemented by digital synchronous ways, and can accomplish the 7(can expand to N) routes E1 data's demultiplexer and multiplexer. The design entry is VHDL and state transition.