JPEG2000熵编码模块的FPGA实现

Hardware Implementation of Entropy Coding in JPEG2000

依据JPEG2000标准中熵编码模块的基本内容,设计并实现了一种"适合VLSI实现"的嵌入式位平面编码硬件结构.通过对算术编码的硬件结构进行相应修改,加入前导零探测模块,达到了一个时钟周期编码一个符号的吞吐率.用Verilog语言在RTL级对熵编码模块进行描述,采用ALTEAR公司的现场可编程门阵列(FPGA)进行仿真验证与综合,结果表明所实现的熵编码模块能够以较小的资源耗费换取编解码时间的有效节约.

Keystone of entropy coding in JPEG2000 is described systemically in this paper. An architecture of bit plane coding suitable for VLSI is presented. The architecture of arithmetic coding procedure is modified. Based on leading zeros detection, symbol can be encoded and decoded within one cycle. The module of entropy coding is described with verilog in RTL. For the series of ALTERA FPGA, the result of synthesis and post-stimulation indicates that the entropy coding module realized by this paper gets efficacious economize of encode and decode time with lesser use of resource.