32位RISC中存储管理单元的设计

On Designing for Chinese Use a MMU(Memory Management Unit) of a 32-bit RISC

多任务处理要求在处理器中集成片上的存储管理单元 ( MMU) ,支持虚拟存储管理 ,通过硬件 MMU把虚地址转换成物理地址。提出了 32位超标量 RISC微处理器的 MMU体系结构 ,论述了逻辑地址到物理地址转换的 3种机制以及相应的存储保护和异常处理 ;着重讨论 TLB( Translation Lookaside Buffer)的设计原则 ,并对其 3种设计结构进行分析比较 ,优化了 TLB的组织结构 ;给出了 MMU的组成、数据通路、控制通路 ,解决了速度瓶颈 ,满足了芯片的设计要求。整个芯片用 TSMC 0 .2 5μm工艺实现 ,芯片面积为 5 mm× 5 mm,主频为 66MHz。

The Aviation Microelectronic Center of NPU(Northwestern Polytechnical University) has recently completed the development of a 32-bit super-scalar RISC microprocessor for filling the need of Chinese military aviation. This paper presents the design of its MMU. Section 1 discusses in detail address translation. Figs.2 and 3 explain respectively page-address-translation flow and block-address-translation flow. In Fig.2, it is worth mentioning that a 52-bit interim virtual address and the Hash function are used to generate the address of page table. Section 2 introduces the memory protection and exception processing mechanisms. As the most important logic in the whole design of MMU, the design of TLB (Translation Lookaside Buffer) is analyzed in detail in section 3; three mapping mechanisms are compared in area, speed and hit rate in order to optimize the TLB logic by tradeoffs. Subsection 4.1 provides the detailed archit-ecture of MMU, including its data path and control path, and the critical timings. Subsection 4.2 analyzes the speed bottleneck of MMU implementation which seriously affects the system performance and proposes some solutions. Section 5 gives a 3-point implementation: (1) the processor contains 3.36 M transistors; (2) the chip is fabricated in a TSMC 0.25 μm CMOS process with 5 metal layers and packaged in a 240-pin CQFP; (3)the die size of the chip is 25 mm 2 and the CPU operating frequency is at least 66 MHz.