浮点数除法器的FPGA实现

Design of Floating-point divider on FPGA

由于在QuartusII中自带的除法运算的兆模块lpm_division的输出结果是以商和余数的形式输出,不能满足应用要求,笔者提出了一种基于FPGA的浮点除法器的硬件实现方法。根据除法的本质是移位相减的原理,及浮点数规格化的要求,采用模块化设计方法分别对各模块进行设计。在MaxplusⅡ上进行综合仿真测试后,证明该模块运算准确、精度高且具有很好的移植性。

There are 'lpm_division' in QuartusII.But it can t apply requirement,because the output have remainder and quotient.It study that the method of floating-point divider based on FPGA-based hardware.Based on the nature of division and the requirement of standardized,design all of module.Test and Comprehensive used MaxplusⅡ.It prove that this module can operate accurately and apply in other filed.The structure is the most focal point in this paper.