SystemC到HDL的研究探讨

The Study of SystemC to HDL

如今,用SystemC进行硬件设计和建模已成为一种趋势。但是,VHDL和Verilog是被公认的业界标准,因此,有时就不可避免要将SystemC转换成VHDL或Verilog。本文介绍了几种比较典型的免费翻译工具,简要阐述了各自的特性并作了一个比较。如果进行较大的设计研究,选择SystemCrafter SC和Agility Compiler比较理想。

Now,using SystemC for hardware design and modeling has become a trend.However,VHDL and Verilog are recognized as the industry standard,and sometimes it is inevitable to convert SystemC to VHDL or Verilog.This paper described some of the typical free translation tools,briefly described the characteristics of theirs,and made a comparison.If it is to carry out the large design and research,choosing SystemCrafter SC and Agility Compiler will be ideal.