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RS编译码的FPGA实现 被引量:1

Implementation of RS Coder and Decoder Using FPGA
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摘要 RS码作为一类强大和被广泛使用的前向纠错码,被广泛应用于数字系统的信道编码方案中。介绍RS码的编码原理和时域迭代译码算法,在此基础上用Verilog HDL设计实现出RS码编码器和译码器。 Reed-Solomon(RS)code is one of the most powerful and widely used coding schemes for FEC.RS code were used in the digital channel coding scheme.In this thesis,the code theory and time-domain iterative decode algorithm of RS code is introduced,RS coder and decoder are designed and implemented in this base with the Verilog HDL.
出处 《舰船电子工程》 2008年第11期107-110,共4页 Ship Electronic Engineering
关键词 RS码 VERILOGHDL FPGA实现 RS code Verilog HDL FPGA implementing
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参考文献3

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同被引文献8

  • 1郑宇驰,周晓方,闵昊.OFDM系统中Viterbi译码器的设计及FPGA验证[J].复旦学报(自然科学版),2005,44(6):923-928. 被引量:5
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