改进的高速可伸缩双域模乘器设计及实现

Design and Implementation of a Modified High Speed Scalable Dual-Field Modular Multiplier

基于多精度双域Montgomery模乘算法实现了一个可伸缩双域模乘器.模乘器处理单元采用新颖的三时钟结构代替传统的双时钟结构缩短关键路径延时,提高了时钟频率.使用SMIC0.18μmCOMS标准单元工艺库综合后,模乘器的时钟频率最大能达到240MHz,计算256bit有限域GF(p)上的模乘只需要0.23μs.

Based on multi-precision dual-field Montgomery modular multiplication algorithm,a scalable dual-field modular multiplier is implemented.Its processing cell replaces conventional dual-clock architecture with a novel triple-clock architecture that shortens the critical path and boosts the clock frequency.The performance is improved so efficiently that it is only 0.23μs @240MHz to compute a 256bit modular multiplication overGF(p)under the SMIC0.18μm CMOS standard cell technology.