摘要
本文介绍一种基于ARM和Internet,采用被动串行配置模式,对FPGA进行动态配置的方法。叙述了被动串行配置模式的时序,并且对使用ARM7TDMI-S控制网络接口芯片,产生配置时序的软硬件设计作了说明。
This paper introduces a method to dynamic configure Altera FPGAs in passive serial mode.Configuration data is sent into FPGA througn ARM and Internet.It detailedly describes the PS configuration clock,and presents the software and hardware design for using ARM7TDMI-S microprocessor controll Ethernet-controlled chip and produce configuration clock.
出处
《吉林工程技术师范学院学报》
2007年第6期22-24,共3页
Journal of Jilin Engineering Normal University