基于DCME算法的RS(255,223)码的译码器实现

Implementing RS(255,223) Decoder Using DCME Algorithm

针对RS(255,223)译码问题的特点,研究了一种新的DCME译码方法。相比于其它修正的Euclid算法,具有无需计算阶数,只需经过2t个时钟周期就可以完成关键方程求解的特点,有效地减少了硬件资源的开销及时序控制的复杂度。以错16位的极限情况为例,完成了RS(255,223)译码器的FPGA实现,给出了译码过程中各步骤的仿真结果。采用此方法设计的RS(255,223)译码器具有控制单元简单、模块结构规则,易于FPGA实现,可用于高速场合等特点。

Section 2 of the full paper explains the design of FPGA(field programmable gate arrays),to be used in our RS(255,223) decoder.Section 3 explains the implementation of the RS(255,223) decoder using FPGA designed by us.The core of section 3 is subsection 3.2,which solves a certain crucial equation using DCME(degree computationless modified Euclid) algorithm.Fig.1 in subsection 3.2 gives simulation results,which show preliminarily that our solution is correct.Figs.2 and 3 in section 3 give further simulation r...