摘要
针对高精度的开关电容电路介绍了一种较为新颖的全数字的时钟发生电路,它是由一串单位延时可控电路延时链级联与门组成的“延时与”电路。与同样用途的时钟发生电路相比,该电路具有下列优点:抗时钟抖动、抗干扰能力强,时钟占空比可调节,延时沿输出时钟与原时钟的下降沿(上升沿)不交叠,能随CMOS工艺特征尺寸减小而结构复用等。
A clock generation circuit for high-resolution switched capacitor circuits is demonstrated in this paper. This clock generator is composed of delay-controlled inverter chain, AND gate and feedback circuits, showing advantage of clock jitter resistance, strict nonoverlapped clocks and its edges compared with the other structures.
出处
《上海电机学院学报》
2005年第3期25-28,共4页
Journal of Shanghai Dianji University
关键词
时钟发生电路
开关电容电路
∑Δ调制器
clock generation circuit
switched-capacitor circuits
∑Δ modulator
