芯片氧化层静电放电击穿模型研究

Research on ESD Breakdown Model in IC Silicon Dioxide Films

提出了芯片门电路硅氧化层静电放电介质击穿的物理模型．并使用该模型讨论了介质击穿场强与介质厚 度的关系,讨论了介质击穿电压与ESD(静电放电)敏感度的尺寸效应,对于厚度为0．01μm、面积为 9．09×10-6 cm2氧化层,其击穿电压约为208 V;若面积不变,厚度缩小为原来的1／10,则其击穿电压降为160 V; 若面积也等比例缩小,则击穿电压降为20 V,其结果是耐ESD的能力大幅度降低．

A physical model of dielectric breakdown was presented in IC silicon dioxide films. It is discussed that the dependence between dielectric field strength and dielectric thickness by using this model, and analyzes the size effect of the dielectric breakdown voltage and ESD pulses. As to a film, if its thickness is 0.04 μm and area is 9.09×10-6 cm2, the breakdown voltage of this film is about 208 V; If keeping its effective area and reducing its thickness to 0.004 μm, its breakdown voltage would become 160 V; If reducing its effective area proportionally, its breakdown voltage is about 20 V, thus its capability of anti-ESD must depress.