摘要
学生对异步时序逻辑电路分析时易出错,现介绍一种利用次态卡诺图分析时序逻辑电路的方法,它简便易行,清晰明了。
Most of the students often make a mistake when they analyze the asynchronous sequential logic circuit. A new way is shown here that we can use the next—state Kanaugh map to solve the problem. It makes the analysis easy and clear.
出处
《淮北职业技术学院学报》
2002年第1期65-67,共3页
Journal of Huaibei Vocational and Technical College
关键词
异步时序电路
卡诺图
逻辑分析
asynchronous sequence circuit
Kanaugh map
Logic analysis
