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METHOD OF HIGH-LEVEL TECHNOLOGY MAPPING BASED ON KNOWLEDGE(RULE)

METHOD OF HIGH-LEVEL TECHNOLOGY MAPPING BASED ON KNOWLEDGE(RULE)
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摘要 This paper studies the linkage problem between the result of high-level synthesis and back-end technology, presents a method of high-level technology mapping based on knowl edge, and studies deeply all of its important links such as knowledge representation, knowledge utility and knowledge acquisition. It includes: (1) present a kind of expanded production about knowledge of circuit structure; (2) present a VHDL-based method to acquire knowledge of tech nology mapping; (3) provide solution control strategy and algorithm of knowledge utility; (4)present a half-automatic maintenance method, which can find redundance and contradiction of knowledge base; (5) present a practical method to embed the algorithm into knowledge system to decrease complexity of knowledge base. A system has been developed and linked with three kinds of technologies, so verified the work of this paper. This paper studies the linkage problem between the result of high-level synthesis and back-end technology, presents a method of high-level technology mapping based on knowledge, and studies deeply all of its important links such as knowledge representation, knowledge utility and knowledge acquisition. It includes: (1) present a kind of expanded production about knowledge of circuit structure; (2) present a VHDL-based method to acquire knowledge of technology mapping; (3) provide solution control strategy and algorithm of knowledge utility; (4) present a half-automatic maintenance method, which can find redundance and contradiction of knowledge base; (5) present a practical method to embed the algorithm into knowledge system to decrease complexity of knowledge base. A system has been developed and linked with three kinds of technologies, so verified the work of this paper.
出处 《Journal of Electronics(China)》 2001年第1期24-31,共8页 电子科学学刊(英文版)
关键词 HIGH-LEVEL synthesis TECHNOLOGY mapping VHDL HIGH-LEVEL TECHNOLOGY map PING KNOWLEDGE base KNOWLEDGE representation High-level synthesis Technology mapping VHDL High-level technology mapping Knowledge base Knowledge representation
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参考文献2

  • 1N.V.Zanden,G. D. MILO.A microarchitecture and logic optimizer,Proc[].of the th Design Automation ConferenceIEEE/ACM Anaheim Convevtion Center.1988
  • 2A.R.Naseer,M. Balakrishnan,et al.Delay minimal mapping RTL structures onto LUT based FPGAs,Field programmable logic and applications,5th International Workshop,FPL’95,Proc[].Oxford UK Aug- Sept.1995

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