一种高速高精度的CMOS比较器的电路

High-speed High-resolution Comparator Circuit

为了满足12位高分辨率的A/D转换器的需要,设计了一种高精度CMOS比较器,采用三级差分比较和一级动态正反馈的Latch结构实现了高比较精度。运用了一种先进的输入失调消除方法,完全实现了输入失调的消除。对该比较器的电路结构、增益、带宽、输入失调消除原理和锁存时间常数进行了分析,并利用Hynix0.5μm CMOS工艺提供的器件模型进行了仿真,在20MHz频率下,比较器的精度达到了400μV,电源电压为5V时,功耗为78μW。该比较器可用于一种10MSPS12位A/D转换器中,也可用于13位以下的其他A/D转换器电路。

To guarantee a 12-bit high resolution for an A/D converter,a precise CMOS comparator consisting of a three-stage differential comparator together with a positive feedback latch is proposed. An advanced method is used to cancel input offset. Circuit structure,gain,bandwidth,the principle of input offset cancellation and latching time constant for the comparator are analyzed. Simulation model is based on 0.5μm CMOS process. The test result shows that the circuit has an accuracy of 400μV at 20MHz,and dissipates only 78μW of power at 5V. The comparator will have been used in a 10MSPS 12-bit A/D converter. The circuit can be also used in less than 13-bit A/D converter.