一个10位逐次逼近式ADC电路

A 10-bit Successive Approximation ADC Circuit

设计了一个10位的逐次逼近式模数转换器。用电阻和电容混合结构来实现模数转换器缩小芯片面积和减小系统复杂度。对模数转化器电路结构进行分析,给出了该模数转换器工作模型,并且设计了一种高速比较器的电路。芯片用0.5μm的CMOS混合信号工艺来仿真和流片,测试结果:在输入信号为200kHz时,信噪失真比62dB,动态范围72dB,有效位达到9.4bit。该逐次逼近式ADC电路已经成功用在消费电子产品中。

A 5-V 10 bit 1MS/s successive approximation analog-to-digital converter (ADC) with hybrid structure is implemented for low-power low-cost CMOS integrated systems. This design is based on a hybrid structure that minimizes the overall chip area and system complexity. The article analyzes the circuit design of ADC and gives the model of ADC. According to the test results,the ADC has a signal-to-noise distortion ratio (SNDR) of 62,and peak spurious free dynamic range (SFDR) of 72dB for a 200 kHz input sine wave at 1MS/s. The effective number of bits (ENOB) is 9.4bit.This ADC is successfully applied in consumer electronic products.