流水线模数转换器系统功耗建模与优化方法

Method for systematic power consumption modeling and optimization of pipeline ADC

针对低功耗应用的需求,对流水线模数转换器(ADC)的系统功耗进行了研究与分析,深入探讨了余量放大器电流、级分辨率分配、热噪声限制、电容缩减系数以及前级采样保持电路等因素对系统功耗的影响.在分析基础上进行了功耗建模,导出系统总功耗.同时,提出采用混合搜索算法来同时优化流水线每一级的精度和单位电容值,实现了一个可以自动完成整个优化过程的CAD工具,应用该工具分别在不同优化条件下对10～15位流水线ADC进行了优化,并给出了14位,100MS.s-1 ADC的具体优化结果.

On the demands of low power applications,the systematic power consumption of pipeline Analog-to-Digital converters(ADC) was researched and analyzed.Some power related factors including the current of the residue amplifiers,the scaling down of the stage accuracy,the thermal noise limitation,the optimization scaling down factor of capacitances as well as the front-end sampling hold circuits were discussed in details.Based on it,the system power consumption modeling was put forwards and the total dominant power consumption was derived.A hybrid search algorithm was employed to optimize the capacitance and resolution of each stage simultaneously.And a CAD tool was developed to implement the whole optimization process.By using it,the system structure of a 10~15 bits pipeline ADCs was optimized.And the results of a 14-bit 100 MS·s-1 pipeline ADC were shown in detail.