高速可配RSA加速器设计与实现

Design and implementation of high-speed configurable RSA accelerator

为实现高速可配RSA硬件加速器,提出了一种基于基—64蒙哥马利算法的模乘器流水线架构及其对应的可配置存储结构。通过五级流水线的并行运算和存储器的灵活配置,可以高效地实现256位到2048位的RSA运算。实验结果表明:与其他相关工作比较,提出的流水线架构能够取得较好的性能和资源消耗比,加速器在模乘器性能和数据吞吐率方面有明显提高。在73 k门硬件资源下,在1024位RSA运算情况下,实现了333 kbps的数据吞吐率。

To implement high-speed configurable RSA accelerator,a pipelined modular multiplier architecture based on radix—64 Montgomery modular multiplication algorithm and its corresponding configurable memory architecture are proposed.With parallel calculation of five-stage pipeline and configurable memory,it fulfills RSA calculation ranging from 256-bit to 2048 bit efficiently.As is shown in experiment,compared with other related works,the proposed pipeline architecture can reach better tradeoff between performance and resource.The accelerator is able to increase the performance of modular multiplier and total data throughput.With 73-kilo gates,it achieves 333 kbps data throughput for 1024-bit RSA calculation.