高性能异或门电路的设计

Design of a novel high performance XOR gate

在分析已发表的典型异或门电路的基础上,提出一种新型高性能的异或门电路,其电路核心部分仅3个晶体管,包括一个改进型互补CMOS反相器和一个NMOS传输门.在TSMC0.18μm CMOS工艺下经HSPICE模拟.结果表明,与已有的异或门电路相比,新设计在速度和功耗延迟积上具有较大的优势.

Based on the analysis of published XOR gate circuits,a novel design of XOR gate was proposed.The key circuit of the proposed XOR gate uses only three transistors which induded a modified version of complementary CMOS inverter and a NMOS pass transistor logic.HSPICE simulation showed that the proposed design of XOR gate has significant advantages in speed and PDP under the TSMC 0.18 μm CMOS technology,as compared to the existing XOR gate circuits.