新型8管一位全加器电路设计

Design of a novel 8-transistor full adder circuit

通过对已有全加器电路的研究与分析,提出了仅需8个晶体管的新型全加器单元.新电路包括2个3管同或门模块和1个选择器模块.在台积电(TSMC)0.18μm互补氧化物半导体(CMOS)工艺器件参数下经电路模拟程序(HSPICE)进行性能测试,与现有典型的全加器相比,新电路在晶体管数目、功耗和功耗延迟积有较大的优势.

Based on the research and analysis of existing full adder circuits,a novel full adder cell used only 8 transistors was proposed.The novel circuit was composed of two 3-XNOR gates and one multiplexer.Compared with the typical full adder circuits,the proposed full adder circuit shows a significant improvement in transistor count power consumption and power delay product by tested with HSPICE simulation based on 0.18 μm CMOS process.