对称加密算法RC5的架构设计与电路实现

Architecture Design and Circuit Implementation of RC5 Symmetric Encryption Algorithm

对RC5对称加密算法的Feistel结构加解密内核电路实现架构展开了研究.在对已有的Feistel流水线设计方法分析的基础上,提出了具有不同结构特点的RC5算法Feistel流水线实现方案,并分析探讨了各自的结构特点.在对几种算法实现结构分析对比的基础上,提出了一种紧凑高效的RC5算法Feistel电路结构,该电路将一个计算轮拆分为两个计算周期完成,对逻辑资源进行高度复用,在不增加任何电路资源条件下实现了RC5加密引擎的全速流水,给出了该结构的仿真数据和可编程逻辑阵列(FPGA)电路实现结果.

The circuit architecture design of Feistel core in RC5symmetric encryption algorithm was described.Based on the pre-existing study of hardware Feistel pipeline implementation methods,different architectures of RC5Feistel core were proposed and discussed.A compact and high efficient RC5Feistel architecture was put forward on the basis of the analysis of the several available implementations in literatures.The proposed architecture divided each encryption/decryption round into two cycles,and the logic modules were fully reused between cycles.The architecture worked at pipelined manner without any extra hardware resources.The simulation and FPGA implementation result were given and discussed.