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一种有符号余数系统2~n缩放方法及VLSI实现

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摘要 数值缩放的高效VLSI实现是余数系统(RNS)应用于数字信号处理(DSP)系统中的关键问题之一.文中首先提出了有符号余数系统数值缩放通用算法,明确给出了在负数情况时修正常量的计算方法.在此基础上给出了一种有符号余数系统2n缩放的高效实现方法,该方法利用中国剩余定理和一个较小的冗余基实现基扩展以获取RNS整数的低n比特信息,并借助所引入的冗余基用奇偶检测完成RNS整数的符号检测,同时还提出了冗余基更新方法及负数情况下冗余通道修正常量计算方法.分析结果表明所提出的RNS数值缩放方法的复杂度仅同RNS的动态范围位宽呈线性关系,并避免了使用查找表(LUT).最后,完成了此方法和基于串行方式的2n缩放算法的VLSI实现,在相同约束条件下该方法的面积和功耗均减小了35%左右,而关键路径延时则减小了12%左右,VLSI版图也表明了该方法具有更简单的芯片内联结构.
出处 《中国科学:信息科学》 CSCD 2010年第6期899-908,共10页 Scientia Sinica(Informationis)
基金 国家自然科学基金(批准号:60873076) 国家高技术研究发展计划(批准号:2007AA01Z291)资助项目
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参考文献21

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