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一种超低功耗5.8GHz双模前置分频器设计 被引量:2

Design of an Ultra Low-power 5.8GHz Dual-Modulus Prescaler
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摘要 基于目前流行的TSPC高速电路,利用TSMC90nm 1P9M 1.2V CMOS工艺设计了高速、低压、低功耗32/33双模前置分频器,其适用于WLAN IEEE802.11a通信标准。运用Mentor Graphics Eldo对该电路进行仿真,仿真结果显示,工作在5.8GHz时功耗仅0.8mW,电路最高的工作频率可达到6.25GHz。 基于目前流行的TSPC高速电路,利用TSMC90nm 1P9M 1.2V CMOS工艺设计了高速、低压、低功耗32/33双模前置分频器,其适用于WLAN IEEE802.11a通信标准。运用Mentor Graphics Eldo对该电路进行仿真,仿真结果显示,工作在5.8GHz时功耗仅0.8mW,电路最高的工作频率可达到6.25GHz。
出处 《电子技术(上海)》 2010年第1期76-77,共2页 Electronic Technology
关键词 双模前置分频器 单相时钟 高速度 低功耗 dual-modulus prescaler TSPC high speed low power consumption
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参考文献6

  • 1杨文荣,曹家麟,冉峰,王键,秦霆镐.一种适用于RF频率合成器的CMOS高速双模前置分频器[J].上海大学学报(自然科学版),2005,11(1):20-23. 被引量:5
  • 2Xiao P.YU,,Manh.DO,,Wei Meng Lim,et al.Design and optimizationof the extended true single-phase clock-based prescaler. IEEE Trans.on Microwave Theory and Techniques . 2006
  • 3Foroudi N,Kwasniewski T A.CMOS high-speed dual -modulus frequency divider for RF frequency synthesis. IEEE Journal of Solid State Circuits . 1995
  • 4Huang Q,Rogenmoser R.Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. IEEE Journal of Solid State Circuits . 1996
  • 5Yuan J,Svensson C.High-speed CMOS circuit technique. IEEE Journal of Solid State Circuits . 1989
  • 6Byungsoo Chang,Joonbae Park,Wonchan Kim.A 1.2GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flop. IEEE Journal of Solid State Circuits . 1996

二级参考文献9

  • 1Lava Christopher, Razavi Behzad. A 2.6 GHz/5.2 GHz frequency synthesizer in 0.4 μm CMOS technology [ J ].IEEE Journal of Solid-state Circuits, 2000, 35(5) :788-794.
  • 2Hung Chih-Ming, Floyd B A, Park, N, et al. Fully integrated 5.35 GHz CMOS VCOs and prescaler [J]. IEEE Trans Microwave Theory Tech, 2001, 44(1):17-22.
  • 3Foroudi N, Kwasniewski T A. CMOS high speed dualmodulus frequency divider for RF frequency synthesis [ J ].IEEE Journal of Solid-state Circuits, 1995, 30(2):93-100.
  • 4Larsson P. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler [J]. IEEE Journal of Solid-state Circuits, 1996, 31(5) :744-748.
  • 5Yuan J, Svenssor C. High-speed CMOS circuit technique[J]. IEEE Journal of Solid-state Circuits, 1989, 24(2):62-70.
  • 6Yang J, Debng G, Hsu J, eta/. New dynamic flip flops for high-speed dual-modulus prescaler [ J]. IEEE Journal of Solid-state Circuits, 1998, 33(10) :62-70.
  • 7Chang B, Park J, Kin W. A 1.2 GHz CMOS dual modulus prescaler using dynamic D-type flip-flops[J]. IEEE Journal of Solid-state Circuits, 1996, 31(5) :749-752.
  • 8Craninckx J, Steyaert M. A 1.75 GHz 3 V dual modulus divider by 128/129 prescaler in 0.7 μm CMOS [J]. IEEEJournal of Solid-state Circuits, 1996, 31(7) :890-897.
  • 9Ahmed A, Shard K. CMOS VCO prescaler cell-based design for RF PLL frequency synthesizers [ A ]. IEEE International Symposium on Circuits and System [ C ].Geneva, Switzerland, 2000. 737-740.

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