GPS软件接收机捕获算法的FPGA仿真

Simulation of acquisition algorithm for GPS software receiver based on FPGA

探讨了GPS软件接收机的前端采集数据结构、C/A码捕获算法原理、Virtex2p开发板原理.为了能在FPGA(可编程门阵列)上实现GPS信号并行捕获算法,采用了补零计算来弥补算法中采样点不基于2N的不足,并且在Simulink环境下运用基于FPGA的应用软件SystemGenerator进行了补零后的并行捕获算法的FFT模块、虚数乘法模块、平方模块等搭建编程.同时采用了Matlab中的M文件将采样数据仿真成模拟信号导入完成仿真实验,并将仿真结果与Matlab结果进行了相应的比较和分析,得到与Matlab结果同样的捕获频率.虽由于补零引起小于1个码元(16个采样点)的采样点误差,但不影响捕获结果,证实了System Generator在FPGA实现捕获算法可行性.

The sample data structure of the global position system(GPS) software receiver radio frequency(RF) front-end,the principle of the GPS C/A code acquisition algorithm,and the principle of Virtex2p are discussed.In order to implement the GPS parallel acquisition algorithm,the method of zero padding is used to overcome the limitation of data which is not based on 2N.Meanwhile,based on the Simulink environment,the software System Generator is used to set up the FFT module,the multiplier of imaginary number,the square module of the improved acquisition algorithm.The input signal is generated by M file from the sample data;two results from Matlab and field programmable gate array(FPGA) are compared and analyzed.It shows that the same acquisition frequency can be obtained in System Generator,and acquisition results are not influenced by the error less than one code(sixteen samples) caused by zero adding.The feasibility of the acquistion algorithm based on FPGA is verified.