一种高效数字滤波器设计方法

High-efficiency Digital Filter Design Method

针对全数字软件接收机中抽取滤波器的设计,提出了一种适合在FPGA内实现的单级积分清洗的滤波器结构,这种结构解决了传统积分梳妆滤波器中可能出现的积分器溢出问题,同时还可进行非整数倍的抽取变换。给出了一种无乘法半带滤波器的IIR实现结构,并对该滤波器性能进行了仿真,结果表明在输出过采样率大于4时基本不会影响系统误码性能。

In this paper,a single-stage integral-clear filter structure for the decimation filter in SDR is proposed,which is appropriate for implementation in FPGA.Such structure not only can solve overflow problem occurred in the integrator of the conventional CIC filter,but also can process non-integral decimation conversion.An IIR implementation structure of non-multiplier half-band filter is presented,and the performance of such structure is simulated,simulation results prove that the filter will not degrade system BER performance when the output decimation rate is larger than four.