基于S5933的高速数据采集卡控制设计

The Control Logic Design of High Speed Data Receiver Based on S5933

讨论基于 S593 3的高速数据采集卡控制逻辑的实现方案。由于要求数据传输率比较高 ,所以使用 S593 3内部 FIFO的 DMA传输 ,使传输达到 PCI局部总线的 3 2位 3 3 MHz;使用 CPL D控制数据的传输使得板卡的成本比较低 ,控制起来相对比较简单 ,由于 CPL D内各个模块之间是并行操作的 ,这使传输速度能够达到 PCI局部总线的速度。

A design method of the control logic of high-speed data receiver card based on S5933 is presented.Because of the need of the high transfer rate,DMA transfer of S5933 is used to reach 32 bit and 33MHz of PC I local bus.The cost of card is lower and the control becomes simple with the us ing of CPLD.The parallel operation of the each module in CPLD makes the transfer rate of card reach the speed of PCI local bus.