快速的平行码临界路径跟踪故障模拟

Fast Fault Simulation of Parallel Pattern Critical Path Tracing

针对平行码临界路径跟踪故障模拟中最费时间的扇出源故障模拟,提出了若干加速技术。通过对电路结构进行的独立扇出分支、扇出源分类及扇出源的最终汇聚门等静态分析,结合对停止线及停止扇出源、测试码标记向量以及扇出源临界性确定前的预处理等动态计算,使得扇出源故障模拟区域及需要故障模拟的扇出源数目大大减少,极大地缩短了整个故障模拟时间。实验结果表明,平行码临界路径跟踪故障模拟算法,对少量和大批的随机码都非常有效,并且随着电路规模增加,其有效性更加明显。

To counter the most expensive stem fault simulation infault simulation of parallel pattern critical path tracing, this paper presents several accelerated techniques. Owing to these techniques, the area for stem fault simulation and the stems needed faultsimulation are all reduced greatly, so that the entire fault simulation time is decreased substantially. Experimental resultsgiven in this paper show that the fault simulation algorithm usingthese techniques is of very high efficiency for both a small amount and a number of random patterns. Especially with the increase of circuit gates, its effectiveness improves obviously.