期刊文献+

0.8μm LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS

0.8μm LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS
下载PDF
导出
摘要 The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submicron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed. The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submicron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.
出处 《Journal of Electronics(China)》 1995年第1期84-89,共6页 电子科学学刊(英文版)
关键词 SUBMICRON LDD DEVICE Simulation RELIABILITY Submicron LDD device Simulation Reliability
  • 相关文献

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部