一种数据保持的高效插值算法及其FPGA实现

An Efficient Algorithm and Its FPGA Implemenation of Data Retention Interpolation

提出了一种数据保持的高效插值算法,该方法首先采用零值内插提高采样率,降低带宽比例因子,再利用数据保持与一级CIC滤波器结合的方法来实现多倍插值。插值滤波器采用多相方法实现,有效地降低数据的处理速率,提高运算的精度。用多相方式实现CIC滤波,可方便实现多路输出,降低对FPGA处理速率的要求。受FPGA硬件资源的限制,多相滤波器中乘法运算采用时分复用方法实现。设计方案在Altera Stratix FPGA上进行仿真验证,并与零值内插进行比较。结果表明该插值法准确可行,且能够减少硬件资源的消耗。

An efficient algorithm of data retention interpolation is proposed in this paper. First of all,zeros interpolation is used to increase the sampling rate and reduce the bandwidth scaling factor. Then,the data retention combining with CIC filter is used to achieve multiple interpolations. The interpolation filter is obtained by using polyphase structure. The polyphase filter can effectively reduce the data processing speed and improve the accuracy of calculation. The polyphase CIC filter can easily achieve multi-channel output. In this way,it can reduce the processing rate of FPGA. In order to overcome the limitations of FPGA resources,TDM multiplier is used in the polyphase filter. This design is simulated in Altera Stratix FPGA,and compared with the zeros interpolation. The results show that this interpolation algorithm is feasible and accurate. Furthermore,this design can reduce hardware resources.