数字可变符号率调制器设计

Design of Digital Variable Symbol Rate Modulator

针对传统可变符号率调制器设计复杂、成本高的缺点,基于重采样数字信号处理技术,提出一种数字连续可变符号率调制器的设计方法。该方法在数字域采用单一固定频率工作时钟,产生符号脉冲、成形滤波脉冲和相移控制字,完成星座映射、脉冲成形滤波和任意采样率转换,以较小的资源消耗实现了符号率连续可变调制。该设计方法已应用于某卫星通信MODEM中,以较低的FPGA资源消耗实现了可变符号率调制。

In order to simplify the design of conventional variable symbol rate modulator,utilizing the resampling signal processing technologies,a new method to design a digital variable symbol rate modulator is proposed.Using a single fixed frequency work clock,the method generates symbol pulse,pulse shaping pulse and control word of phase shift,and then carries out the constellation mapping,pulse shaping filtering and arbitrary sample rate conversion with small consumption of resources.The method has been used to design the satellite communication MODEMs and realized variable symbol rate modulation on small consumption of FPGA resources.