基于SOI材料α-Si:H TFTs的制作和特性研究(英文)

Focused fabrication and characteristics of α-Si:H TFTs based on silicon-on-insulator materials

采用RF-PECVD系统在SOI材料上制作α-Si:H TFT,纳米非晶硅薄膜厚度为98nm,沟道长宽比为10μm/40μm。用扫描电子显微镜、X射线衍射和拉曼光谱等检测方法对不同退火温度下的氢化非晶硅薄膜形貌进行了表征。采用CMOS工艺、各向异性腐蚀溶液EPW、射频溅射技术和等离子体刻蚀等工艺实现α-Si:H TFT的制作。在给出一般α-Si:H TFT特性分析和实验结果的基础上,又采用建模方式对α-Si:H TFT出现的负阻特性进行研究。提取纳米氢化非晶硅薄膜与栅氧化层界面处能带图的结果表明,在靠近漏端0.5μm范围内,漏压由6V增加到30V时,随漏压的增加,价带能量逐渐下降。研究结果表明,距离漏端0.5μm范围内的压降导致负阻特性产生。

In this work,hydrogenated amorphous silicon thin film transistors(α-Si:H TFTs)with the 98 nm thick nanoα-Si:H thin film and the channel aspect ratio 10μm/40μm are demonstrated,which are based on silicon-on-insulator(SOI)materials and fabricated by RF-PECVD system.The methods,SEM,XRD as well as Raman spectra,are employed to characterize the morphologic and structural properties of the nanoα-Si:H thin film at different annealing temperatures.CMOS processing,anisotropic etching solution EPW,radio frequency spurting and plasma etching techniques are adopted to fabricateα-Si:H TFTs together with IDS-VDScharacteristics.Besides ubiquitous characteristics ofα-Si:H TFTs,the simulation model,allowing for energy balance transport mechanism,is established to specially investigate negative resistance phenomena occurred during experiments.The results from the extraction of the energy band diagram at the interface between the nanoα-Si:H thin film and gate oxide indicate that the valence band energy decreases with the drain voltage ascending from 6V to 30 Vadjacent to the drain within 0.5μm.All these demonstrate that the fallen voltage close to the drain within 0.5μm is responsible for the negative resistance characteristics.