摘要
针对多核流应用处理器中存在的缓存效率低下和一致性问题,提出了数据流应用的流水化分割处理方案,在此基础上提出了一种基于一级私有缓存和二级共有缓存的混合型缓存结构,并深入分析了该结构运行过程中的完整性和一致性问题.通过对常用的FIR、FFT等DSP算法的验证,该高速缓存结构以一定的面积开销将访问下级缓存的可能性降低30%左右,显著降低了流应用的运行时间.
To address the low performance and coherence problem in multicore stream processors,this paper proposes a pipeline with stream-based architecture.A hybrid cache system with private first-level cache and shared second-level is also introduced based on the architecture. We analysis the consistency and coherency of the architecture and then verify it on DSP algorithms such as FIR and FFT.According to the result,although the area is increased,the memory access time of the new system decreases by 30%.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第2期1-4,9,共5页
Microelectronics & Computer
基金
国家自然科学基金面上项目(61176037)
关键词
流处理器
高速缓存
混合一致性协议
stream-based processor
cache
hybrid coherence protocol