一种优化低电压SRAM灵敏放大器时序的4T双复制位线延迟技术

A4T Dual Replica-Bitline Delay Technique ForprocessVariation-Tolerant Low Voltage SRAM Sense Amplifier Timing

提出一种减少SRAM存取时间的4T双复制位线延迟技术.该技术主要降低灵敏放大器使能信号的时序变化.该设计通过增加另外一根复制位线并提出一种新的4T复制单元,以优化低电压SRAM灵敏放大器的时序.TSMC 65nm工艺仿真结果表明,在0.6V电源电压下,与传统复制位线设计相比,该技术的灵敏放大器使能信号时序的标准偏差降低30.8%,其读周期减少12.3%.除此之外,由于4T复制单元的MOS管数与传统复制单元相比降低1/3,减小了整体面积开销.

A 4Tdual replica-bitline delay technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed.This strategy suppresses the timing variation by adding one another replica-bitline and introducing a novel 4Treplica cell which has 4MOS transistors.At the supply voltage of 0.6V,the simulation results show that the standard deviation of the SA-enable timing and cycle time with the proposed technique is30.8% and 12.3% smaller than that with a conventional RBL technique in Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology respectively.Moreover,for the MOS number of 4Treplica cell is 1/3smaller than conventional replica cell,it will reduce the overall area overhead.